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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT6323A Programmable ripple counter with oscillator; 3-state
Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
FEATURES * 8-pin space saving package * Programmable 3-stage ripple counter * Suitable for over-tone crystal application up to 50 MHz (VCC = 5 V 10%) * 3-state output buffer * Two internal capacitors * Recommended operating range for use with third overtone crystals 3 to 6 V * Oscillator stop function (MR) * Output capability: bus driver (15 LSTTL) * ICC category: MSI. APPLICATIONS * Control counters * Timers * Frequency dividers * Time-delay circuits * CIO (Compact Integrated Oscillator) * Third-overtone crystal operation. Notes GENERAL DESCRIPTION The HC/HCT6323A are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT6323A are oscillators designed for quartz crystal combined with a programmable 3-state counter, a 3-state output buffer and an overriding asynchronous master reset (MR). With the two select inputs S1 and S2 the counter can be switched in the divide-by-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The oscillator is designed to operate either in the fundamental or third overtone mode depending on the crystal and external components applied. On-chip September 1993 CPD SYMBOL tPHL/tPLH PARAMETER propagation delay X1 to OUT (S1 = S2 = LOW) maximum clock frequency input capacitance except X1 and X2 power dissipation capacitance per package capacitors minimize external component count for third overtone crystal applications. The oscillator may be replaced by an external clock signal at input X1. In this event the other oscillator pin (X2) must be floating. The counter advances on the negative-going transition of X1. A LOW level on MR resets the counter, stops the oscillator QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns.
74HC/HCT6323A
and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.
TYP. CONDITIONS HC CL = 15 pF; VCC = 5 V 17 HCT 17 ns UNIT
fmax CI
90 3.5 +1; notes 1 and 2 +2; notes 1 and 2 +4; notes 1 and 2 +8; notes 1 and 2 54 42 36 33
90 3.5 54 42 36 33
MHz pF pF pF pF pF
1. CPD is used to determine the dynamic power dissipation (PD in W): PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: fi = input frequency in MHz; fo = output frequency in MHz. VCC = supply voltage in V; CL = output load capacitance in pF. Ipull-up = pull-up currents in A. 2. For HC and HCT an external clock is applied to X1 with: tr = tf 6 ns, Vi is GND to VCC, MR = HIGH Ipull-up is the summation of -II (A) of S1 and S2 inputs at the LOW state. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT6323AD PACKAGE PINS 8 PIN POSITION SO MATERIAL plastic CODE SOT96
2
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
PINNING SYMBOL OUT S1 - S2 GND MR X2 X1 VCC PIN 1 3, 2 4 5 6 7 8 DESCRIPTION counter output mode select inputs for divide by 1, 2, 4 or 8 ground (0 V) master reset (active LOW) oscillator pin clock input/oscillator pin positive supply S1 0 0 1 1 FUNCTION TABLE INPUTS S2 0 1 0 1
74HC/HCT6323A
OUTPUTS OUT fi fi/2 fi/4 fi/8
6
handbook, halfpage handbook, halfpage
OUT S2 S1 GND
1 2
8 7
VCC X1 X2 MR 7 5
X1 CP MR 3 2 CD S1 S2
X2
6323A
3 4
MBA343
6 5
OUT
MBA344
1
Fig.1 Pin configuration.
Fig.2 IEC logic symbol.
6
handbook, full pagewidth
X2 7 X1 CP MR
MBA350
3 - STAGE BINARY COUNTER AND DECODER S1 3 S2 2 OUT 1
5
CD
Fig.3 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
74HC/HCT6323A
handbook, full pagewidth
X2 X1 7 pF VCC 7 pF CP Q
(1) (1)
CP Q FF R
CP Q FF R
FF R
V CC
DECODER VCC VCC MR S1 S2 VCC OUT
MBA349
Internal capacitors typical 7 pF each. Including stray capacitors on pin X1 and X2, total capacitance will be typical 12 pF per pin.
Fig.4 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: non-standard; bus driver (except for X2) ICC category: MSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HC Tamb(C) SYMBOL PARAMETER MIN VIH HIGH level input voltage MR, X1 input LOW level input voltage MR, X1 input HIGH level output voltage X2 output 1.5 3.15 4.2 - - - 3.98 5.48 3.98 5.48 1.9 4.4 5.9 1.9 4.4 5.9 VOH HIGH level output voltage OUT HIGH level output voltage OUT LOW level output voltage X2 output 1.9 4.4 5.9 3.98 5.48 - - - - - VOL LOW level output voltage OUT - - - 25 TYP MAX 1.2 2.4 3.2 0.8 2.1 2.8 - - - - 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - - - - 0 0 0 0 0 0 - - - 0.5 1.35 1.80 - - - - - - - - - - - - - - - 0.26 0.26 0.1 0.1 0.1 0.1 0.1 0.1 -40 to 85 MIN 1.5 3.15 4.2 - - - 3.84 5.34 3.84 5.34 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 3.84 5.34 - - - - - - - - - - - 0.5 1.35 1.8 - - - - - - - - - - - - - - - 0.33 0.33 0.1 0.1 0.1 0.1 0.1 0.1 -40 to 125 UNIT V CC (V) MAX MIN MAX 1.50 - 3.15 - 4.20 - - - - 3.7 5.2 3.7 5.2 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 3.7 5.2 - - - - - - - - 0.5 1.35 1.8 - - - - - - - - - - - - - - - 0.4 0.4 0.1 0.1 0.1 0.1 0.1 0.1 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
74HC/HCT6323A
TEST CONDITION VI OTHER
VIL
VOH
X1 = GND and MR = VCC X1 = VCC and MR = GND X1 = GND and MR = VCC X1 = VCC and MR = GND VIH or VIL
IO = -2.6 mA IO = -3.3 mA IO = -2.6 mA IO = -3.3 mA -IO = 20 A IO = -20 A IO = -20 A IO = -20 A IO = -20 A IO = -20 A IO = -20 A IO = -20 A IO = -20 A IO = -6 mA IO = -7.8 mA IO = 2.6 mA IO = 3.3 mA IO = 20 A IO = 20 A IO = 20 A IO = 20 A IO = 20 A IO = 20 A
VOH
VIH or VIL
VOL
X1 = VCC and MR = VCC X1 = VCC and MR = VCC VIH or VIL
September 1993
5
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
Tamb(C) SYMBOL PARAMETER MIN VOL LOW level output voltage OUT input leakage current X1 input pull-up current S1, S2 and MR quiescent supply current - - - 25 TYP MAX - - - 0.26 0.26 0.1 - - - -40 to 85 MIN -40 to 125 UNIT V CC (V) MAX MIN MAX - - - 0.4 0.4 1 V V A 4.5 6.0 6.0
74HC/HCT6323A
TEST CONDITION VI VIH or VIL OTHER IO = 6 mA IO = 7.8 mA
0.33 0.33 1
ILI
MR = VCC S1 = VCC S2 = VCC GND see Fig.11 and Fig.12 IO = 0
-II
5
30
100
-
-
-
-
A
6.0
ICC
-
-
8
-
80
-
160
A
6.0
VCC or GND
September 1993
6
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER MIN tPHL/tPLH propagation - delay X1 to - OUT divide by 1 - propagation - delay X1 to - OUT divide by 2 - propagation - delay X1 to - OUT divide by 4 - propagation - delay X1 to - OUT divide by 8 - 3-state output disable time MR to OUT 3-state output enable time MR to OUT 3-state output enable time MR to OUT output transition time clock pulse width X1, HIGH or LOW master reset pulse width MR; LOW removal time MR to X1 - - - - - - - - - - - - 50 10 9 80 16 14 100 20 17 25 TYP 61 22 19 74 27 23 91 33 28 105 38 32 75 15 13 36 13 11 61 22 19 14 5 4 17 6.0 5 22 8 7 19 7 6.0 17 85 100 MAX 185 37 31 235 47 40 285 57 48 335 67 57 150 30 26 150 30 26 200 40 34 60 12 10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 60 12 10 100 20 17 125 25 21 8 40 47 -40 to 85 MIN MAX 230 46 39 290 58 49 355 71 60 415 83 71 185 37 31 185 37 31 250 50 43 75 15 13 - - - - - - - - - - - - -40 to 125 MIN - - - - - - - - - - - - - - - - - - - - - - - - 75 15 13 120 24 20 150 30 26 6.6 33 39 MAX 275 55 47 350 70 60 425 85 72 500 100 85 225 45 38 225 45 38 300 60 51 90 19 15 - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz UNIT
74HC/HCT6323A
TEST CONDITION VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 VI Fig.7 OTHER S1 = GND S2 = GND S1 = GND S2 = VCC S1 = VCC S2 = GND S1 = VCC S2 = VCC
tPHL/tPLH
Fig.7
tPHL/tPLH
Fig.7
tPHL/tPLH
Fig.7
tPLZ/tPHZ
Fig.8
tPZL
Fig.8
tPZH
Fig.8
note 1
tTHL/tTLH
Fig.7
tW
Fig.7
tW
Fig.9
trem
Fig.9
fmax
maximum clock 10 pulse frequency 50 59
Fig.7
Note to the 74HC AC Characteristics 1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
September 1993
7
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver (except for X2). ICC category: MSI. Voltages are referenced to GND (ground = 0 V).
74HC/HCT6323A
Tamb (C) SYMBOL PARAMETER MIN VIH HIGH level input voltage MR, S1 and S2 inputs LOW level input voltage MR, S1 and S2 inputs HIGH level input voltage X1 input LOW level input voltage X1 input HIGH level output voltage X2 output 2.0 - 25 TYP MAX - -40 to 85 MIN 2.0 MAX - -40 to 125 MIN 2.0 - UNIT V CC (V) MAX V 4.5 to 5.5 4.5 to 5.5 4.5 5.5 4.5 5.5 4.5
TEST CONDITION VI OTHER
VIL
-
-
0.8
-
0.8
-
0.8
V
VIH
3.15 3.85 - - 3.98
- - - - -
- - 1.35 1.65 -
3.15 3.85 - - 3.84
- - 1.35 1.65 -
3.15 3.85 - - 3.7
- - 1.35 1.65 -
V V V V V
VIL
VOH
X1 = GND and MR = VCC
IO = -2.6 mA
3.98
-
-
3.84
-
3.7
-
V
4.5
IO = -2.6 mA X1 = VCC and MR = GND X1 = GND and MR = VCC IO = -20 A
4.4
4.5
-
4.4
-
4.4
-
V
4.5
4.4
4.5
-
4.4
-
4.4
-
V
4.5
IO = -20 mA X1 = VCC and MR = GND VIH or VIL IO = -20 A
VOH
HIGH level output voltage OUT HIGH level output voltage OUT
4.4
4.5
-
4.4
-
4.4
-
V
4.5
VOH
3.98
-
-
3.84
-
3.7
-
V
4.5
VIH or VIL
IO = -6 mA
September 1993
8
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
Tamb (C) SYMBOL PARAMETER MIN VOL LOW level output voltage X2 output - - 25 TYP MAX 0.26 - -40 to 85 MIN MAX 0.33 -40 to 125 MIN -
74HC/HCT6323A
TEST CONDITION UNIT V CC (V) MAX V 4.5 VI X1 = VCC and MR = VCC X1 = VCC and MR = VCC VIH or VIL OTHER IO = 2.6 mA
0.4
-
0
0.1
-
0.1
-
0.1
V
4.5
IO = 20 A
VOL
LOW level output voltage OUT LOW level output voltage OUT input leakage current input pull-up current S1, S2 and MR quiescent supply current additional quiescent supply current per input pin for unit load coefficient is 1
-
0
0.1
-
0.1
-
0.1
V
4.5
IO = 20 A
VOL
-
-
0.26
-
0.33
-
0.4
V
4.5
VIH or VIL
IO = 6 mA
ILI
-
-
0.1
-
1.0
-
1.0
A
5.5
MR = VCC; S1 = VCC; S2 = VCC GND see Fig.11 and Fig.12 Io = 0 other inputs at VCC or GND; Io = 0; (note 1)
-II
5
25
100
-
-
-
-
A
5.5
ICC ICC
- -
- 100
8 360
- -
80 450
- -
160 490
A A
5.5 5.5
VCC or GND VCC or GND
Note to the HCT DC Characteristics 1. The value of additional quiescent supply current (ICC) for unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT INPUT MR, S1, S2 UNIT LOAD COEFFICIENT 0.40
September 1993
9
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) SYMBOL PARAMETER MIN tPHL/tPLH propagation delay X1 to OUT divide-by-1 propagation delay X1 to OUT divide-by-2 propagation delay X1 to OUT divide-by-4 propagation delay X1 to OUT divide-by-8 3-state output disable time MR to OUT 3-state output enable time MR to OUT 3-state output enable time MR to OUT output transition time clock pulse width X1, HIGH or LOW master reset pulse width MR; LOW removal time MR to X1 - 25 TYP 24 MAX 40 - -40 to 85 MIN MAX 50 -40 to 125 MIN - MAX 60 ns UNIT
74HC/HCT6323A
TEST CONDITION VCC (V) 4.5 VI Fig.7 OTHER S1 = GND S2 = GND
tPHL/tPLH
-
29
50
-
62
-
75
ns
4.5
Fig.7
S1 = GND S2 = VCC
tPHL/tPLH
-
35
60
-
75
-
90
ns
4.5
Fig.7
S1 = VCC S2 = GND
tPHL/tPLH
-
40
70
-
87
-
105
ns
4.5
Fig.7
S1 = VCC S2 = VCC
tPLZ/tPHZ
-
21
35
-
43
-
52
ns
4.5
Fig.8
tPZ
-
16
30
-
37
-
45
ns
4.5
Fig.8
tPZH
-
22
38
-
47
-
57
ns
4.5
Fig.8
see note 1
tTHL/tTLH tW
- 10
5 6
12 -
- 12
15 -
- 15
19 -
ns ns
4.5 4.5
Fig.7 Fig.7
tW
16
8
-
20
-
24
-
ns
4.5
Fig.9
trem fmax
24
12 85
- -
30 40
- -
36 33
- -
ns MHz
4.5 4.5
Fig.9 Fig.7
maximum clock 50 pulse frequency
Note to the 74HCT AC Characteristics 1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH.
September 1993
10
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
74HC/HCT6323A
handbook, halfpage gfs
24
MBA331
(mA/V) 20
handbook, halfpage
R bias = 560 k 16 VCC 12
0.47 F vi (f = 1 kHz)
input
output 100 F 8 A io GND
MGA645
4 0
0
1
2
3
4
5 6 VCC (V)
Fig.5
Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also Fig.6); MR = HIGH.
Fig.6
Typical forward transconductance gfs as a function of the supply voltage Vcc at Tamb = 25 C.
handbook, full pagewidth
1/f max V M (1) tW
X1 INPUT
t PHL
t PLH
OUT OUTPUT
V M (1) t THL t TLH
MBA318
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the clock (X1) to output (OUT) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.
September 1993
11
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
74HC/HCT6323A
handbook, full pagewidth
tf 90 % MR INPUT V M (1) 10 % t PLZ OUTPUT LOW - to - OFF OFF - to - LOW t PHZ OUTPUT HIGH - to - OFF OFF - to - HIGH outputs enabled 90 %
tr
t PZL V M (1) t PZH V M (1) outputs disabled outputs enabled
MBA319
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the input MR to output OUT, 3-state enable and disable times.
handbook, halfpage
tW VM (1)
MR INPUT
t rem
X1 INPUT
V M (1)
MBA323
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the MR minimum pulse width and MR to X1 removal time.
September 1993
12
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
APPLICATION INFORMATION
74HC/HCT6323A
handbook, halfpage
40
MBA347
-II (A)
VCC = 6 V
30
handbook, halfpage
5
6323A
MR
20 4.3 V
10
MBA348
2V 0 0 1 2 3 4 5 VI (V) The input pull-up current is used to create a power-on delay time at MR. 6
Fig.10 Power-on reset.
Fig.11 Typical input pull-up current as a function of the input voltage (VI).
Table 1
Typical application values R2 (k) 4.7 2.2 1 C1 (pF) C2 (pF)
f (MHz) 1
MBA346
47 to 68 47 to 68 33 33
50 handbook, halfpage -II (A) 40
10 25
30
Table 2
Typical Application Values Rbias (k) 3.0 C1 (pF) 4.7
f (MHz)
20 VI = 0 V 10
50
0
1
2
3
4
5
6 VCC (V)
Fig.12 Typical input pull-up current as a function of the supply voltage (VCC).
September 1993
13
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
74HC/HCT6323A
handbook, halfpage
MR (from logic)
handbook, halfpage
MR (from logic)
7
X1 X2 R bias 100 k to 1 M 6
7
X1 X2 R bias 6
R2 2.2 k C2
MBA328 - 1
3 k
C1
22 to 37 pF
100 pF
C1
1 to 10 pF (optional)
MBA329 - 1
Above 5 MHz replace R2 by a capacitor of half the value of C2. CL at which a crystal is specified (or adjusted) equals for this application C1 . C2/C1 + C2.
Applicable for third overtone crystals (lower damping resistance at the third harmonic frequency) at typical 50 MHz. For lower frequencies extra load capacitors must be supplied, or increase bias resistor.
Fig.13 Typical setup for a crystal oscillator operating in the fundamental mode (1 MHz to 25 MHz).
Fig.14 Typical set-up for a crystal oscillator operating in the third overtone mode without the use of an inductor.
September 1993
14
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
Typical Crystal Oscillator In Fig.13, R2 is the power limiting resistor. For starting and maintaining oscillation a minimum transconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 k. The oscillator has been designed to operate over a wide frequency spectrum, for quartz crystals operating in the fundamental mode and in the overtone mode. The circuit is a Pierce type oscillator and requires a minimum of external components. There are two on-chip capacitors, X1 and X2, of approximately 7 pF. Together with the stray and input capacitance the value becomes 12 pF for 8-pin SO packages. These values are convenient and make it possible to run the oscillator in the third overtone without external capacitors applied. If a certain frequency is chosen, the IC parameters, as forward transconductance, and the crystal parameters such as the motional resistances R1 (fundamental), R3 (third overtone) and R5 (fifth overtone), are of paramount importance. Also the values of the external components as Rs (series resistance) and the crystal load capacitances play an important role. Especially in overtone mode oscillations, Rb (bias resistance) and the load capacitance values are very important. Considerations for Fundamental Oscillator: In the fundamental oscillator mode, the Rb has only the function of biasing the inverter stage, so that it operates as an amplifier with a phase shift of approximately 180. The value must be high, i.e. 100 k up to 10 M. The load capacitors C1 and C2, must have a value that is suitable for the crystal being used. The crystal is designed for a certain frequency having a specific load capacitance. C1 can be used to trim the oscillation frequency. The series resistance reduces the total loop gain. One function of it is therefore to reduce the power dissipation in the crystal. Rs also suppresses overtone oscillations and introduces a phase shift over a broad frequency range. This is of less concern provided Rs is not too high a value. Note A combination of a small load capacitor value and a small series resistance, may cause a third overtone oscillation.
74HC/HCT6323A
Considerations for Third-overtone Oscillator: In the overtone configuration, series resistance is no longer applied. This is essential otherwise the gain for third overtone can be too small for oscillation. A simple solution to suppress the fundamental oscillation, is to spoil the crystal fundamental activity. By dramatically reducing the value of the bias resistor of the inverting stage, and applying small load capacitors, it is possible to have an insufficient phase in the total loop for fundamental oscillation. However the phase for third overtone is good. It can be explained by the Rb x Cl time constant. During oscillation the crystal with the load capacitors cause a phase shift of 180. Because Rb is parallel with the crystal (no Rs), Rb spoils the phase for fundamental. Rb x Cl must be of a value, that it is not spoiling the phase for third overtone too much. Because third overtone is a 3 times higher frequency than the fundamental, the Rb x Cl cannot 'maintain' the higher third overtone frequency, which results in a less spoiled overtone phase. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
15

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